DRAMTMG7_SHADOW (DDRC) Register Description
| Register Name | DRAMTMG7_SHADOW |
|---|---|
| Offset Address | 0x000000211C |
| Absolute Address | 0x00FD07211C (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000202 |
| Description | SDRAM Timing Shadow Register 7 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG7_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| t_ckpde | 11:8 | rwNormal read/write | 0x2 | LPDDR3/LPDDR4: This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - LPDDR3: 2 - LPDDR4: tCKCKEL Program this to recommended value divided by two and round it up to next integer. |
| t_ckpdx | 3:0 | rwNormal read/write | 0x2 | LPDDR3/LPDDR4: This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - LPDDR3: 2 - LPDDR4: 2 Program this to recommended value divided by two and round it up to next integer. |