DRAMTMG8_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRAMTMG8_SHADOW (DDRC) Register Description

Register NameDRAMTMG8_SHADOW
Offset Address0x0000002120
Absolute Address 0x00FD072120 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x03034405
DescriptionSDRAM Timing Shadow Register 8

This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG8_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
t_xs_fast_x3230:24rwNormal read/write0x3tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, and RTP).
Program this to the above value divided by 2 and round up to next integer value.
Unit: Multiples of 32 clocks.
Note: This is applicable to only ZQCL/ZQCS commands.
Note: Ensure this is less than or equal to t_xs_x32.
t_xs_abort_x3222:16rwNormal read/write0x3tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort.
Program this to the above value divided by 2 and round up to next integer value.
Unit: Multiples of 32 clocks.
Note: Ensure this is less than or equal to t_xs_x32.
t_xs_dll_x3214:8rwNormal read/write0x44tXSDLL: Exit Self Refresh to commands requiring a locked DLL.
Program this to the above value divided by 2 and round up to next integer value.
Unit: Multiples of 32 clocks.
Note: Used only for DDR3 and DDR4 SDRAMs.
t_xs_x32 6:0rwNormal read/write0x5tXS: Exit Self Refresh to commands not requiring a locked DLL.
Program this to the above value divided by 2 and round up to next integer value.
Unit: Multiples of 32 clocks.
Note: Used only for DDR3 and DDR4 SDRAMs.