DRAMTMG8_SHADOW (DDRC) Register Description
Register Name | DRAMTMG8_SHADOW |
---|---|
Offset Address | 0x0000002120 |
Absolute Address | 0x00FD072120 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x03034405 |
Description | SDRAM Timing Shadow Register 8 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG8_SHADOW (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
t_xs_fast_x32 | 30:24 | rwNormal read/write | 0x3 | tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, and RTP). Program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. |
t_xs_abort_x32 | 22:16 | rwNormal read/write | 0x3 | tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. Program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Ensure this is less than or equal to t_xs_x32. |
t_xs_dll_x32 | 14:8 | rwNormal read/write | 0x44 | tXSDLL: Exit Self Refresh to commands requiring a locked DLL. Program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR3 and DDR4 SDRAMs. |
t_xs_x32 | 6:0 | rwNormal read/write | 0x5 | tXS: Exit Self Refresh to commands not requiring a locked DLL. Program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR3 and DDR4 SDRAMs. |