DRCR (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRCR (R5_DBG_0) Register Description

Register NameDRCR
Offset Address0x0000000090
Absolute Address 0x00FEBF0090 (CORESIGHT_R5_DBG_0)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionDebug Run Control Register

DRCR (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Cancel_memory_requests 4woWrite-only0If 1 is written to this bit, the processor abandons any pending memorytransactions until it can enter debug state. Debug state entry is the acknowledge event that clears this request. Abandoned transactions have the following behavior:
. abandoned stores might write an Unpredictable value to the target address
. abandoned loads return an Unpredictable value to the register bank.
An abandoned transaction does not cause any exception. Additional instruction fetches or data accesses after the processor entered debug state have an Unpredictable behavior.
This bit enables the debugger to progress on a deadlock so the processor can enter debug state. For a debug state entry to occur, a halting debug event must be requested before this bit is set. If you write a 1 to this bit when DBGENm is LOW, the write has no effect.
Clear_sticky_pipeline_advance 3woWrite-only0Writing a 1 to this bit clears DSCR[25].
Clear_sticky_exceptions 2woWrite-only0Writing a 1 to this bit clears DSCR[8:6].
Restart_request 1woWrite-only0Writing a 1 to this bit requests that the processor leaves debug state. This request is held until the processor exits debug state. When the debugger makes this request, it polls DSCR[1] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is not in debug state.
Halt_request 0woWrite-only0Writing a 1 to this bit triggers a halting debug event, that is, a request that the processor enters debug state. This request is held until the debug state entry occurs. When the debugger makes this request, it must poll DSCR[0] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is already in debug state.