DSCCR (R5_DBG_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DSCCR (R5_DBG_1) Register Description

Register NameDSCCR
Offset Address0x0000000028
Absolute Address 0x00FEBF2028 (CORESIGHT_R5_DBG_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDebug State Cache Control Register

DSCCR (R5_DBG_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
nWT 2rwNormal read/write0x0Not write-through:
1 = normal operation of regions marked as write-back in debug state
0 = force write-through behavior for regions marked as write-back in debug state
nIL 1rwNormal read/write0x0Instruction cache line-fill:
1 = normal operation of L1 instruction cache in debug state
0 = L1 instruction cache line-fills disabled in debug state
nDL 0rwNormal read/write0x0Data cache line-fill:
1 = normal operation of L1 data cache in debug state
0 = L1 data cache line-fills disabled in debug state