DSCRext (R5_DBG_0) Register Description
| Register Name | DSCRext |
|---|---|
| Offset Address | 0x0000000088 |
| Absolute Address | 0x00FEBF0088 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000002 |
| Description | Debug Status and Control Register |
DSCRext (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| RXfull | 30 | roRead-only | 0x0 | The RXfull flag: 0 = Read-DTR, DTRRX, empty. 1 = Read-DTR, DTRRX, full. When set, this flag indicates to the processor that there is data available to read at the DTRRXint. It is automatically set on writes to the DTRRXext by the debugger, and is cleared when the processor reads the CP14 DTR. If the flag is not set, the DTRRXint returns an Unpredictable value. |
| TXfull | 29 | roRead-only | 0x0 | The TXfull flag: 0 = Write-DTR, DTRTX, empty. 1 = Write-DTR, DTRTX, full. When clear, this flag indicates to the processor that the DTRTXint is ready to receive data. It is automatically cleared on reads ofthe DTRTXext by the debugger, and is set when the processor writes to the CP14 DTR. If this bit is set and the processor attempts to write to the DTRTXint, the register contents are overwritten and the TXfull flag remains set. |
| PipeAdv | 25 | roRead-only | 0x0 | Sticky pipeline advance read-only bit. This bit enables the debugger to detectwhether the processor is idle. In some situations, this might mean that the system bus port is deadlocked. This bit is set to 1 when the processor pipeline retires one instruction. It is cleared by a write to DRCR[3]. 0 = no instruction has completed execution since the last time this bit was cleared 1 = an instruction has completed execution since the last time this bit was cleared |
| InstrCompl_l | 24 | roRead-only | 0x0 | Instruction complete read-only bit. Thisflag determines whether the processor has completed execution of an instruction issued through the APB port. 0 = processor is executing an instruction fetched from the ITR Register 1 = processor is not executing an instruction fetched from the ITR Register. When the APB port reads the DSCR and this bit is clear, then a subsequent write to the ITR Register is ignored unless DSCR[21:20] is not equal to 0. If DSCR[21:20] is not equal to 0, the ITR write stalls until the processor completes execution of the current instruction. If the processor is not in debug state, then the value read for this flag is Unpredictable. The flag is set to 1 on entry to debug state. |
| ExtDCCmode | 21:20 | rwNormal read/write | 0x0 | DTR access mode. You can use this field to optimize DTR traffic between a debugger and the processor. b00 = Non-blocking mode b01 = Stall mode b10 = Fast mode b11 = Reserved. Note . This field only affects the behavior ofDSCRext, DTRRXext, DTRTXext, and ITR accesses through the APB port, and not through CP14 debug instructions. . Non-blocking mode is the default setting. Improper use of the other modes might result in the debug access bus becoming deadlocked. |
| ADAdiscard | 19 | roRead-only | 0x0 | The Asynchronous Aborts Discarded bit is set when the processor is in debug state and is cleared on exit from debug state. While this bit is set, the processor does not take asynchronous Data Aborts, instead, the sticky asynchronous Data Abort bit is set to 1. 0 = do not discard asynchronous Data Aborts 1 = discard asynchronous Data Aborts and set ADABORT_I. |
| NS | 18 | roRead-only | 0x0 | reserved |
| SPNIDdis | 17 | roRead-only | 0x0 | This bit is the inverse of bit [6] of the AUTHSTATUS |
| SPIDdis | 16 | roRead-only | 0x0 | This bit is the inverse of bit [4] of the AUTHSTATUS |
| MDBGen | 15 | rwNormal read/write | 0x0 | The Monitor debug-mode enable bit: 0 = Monitor debug-mode disabled 1 = Monitor debug-mode enabled. If Halting debug-mode is enabled through bit [14], then the processor is in Halting debug-mode regardless of the value of bit [15]. If the external interface input DBGENm is LOW, this bit reads as 0. The programmed value is masked until DBGENm is HIGH, and at that time the read value reverts to the programmed value. |
| HDBGen | 14 | rwNormal read/write | 0x0 | The Halting debug-mode enable bit: 0 = Halting debug-mode disabled 1 = Halting debug-mode enabled. If the external interface input DBGENm is LOW, this bit reads as 0. The programmed value is masked until DBGENm is HIGH, and at that time the read value reverts to the programmed value. |
| ITRen | 13 | rwNormal read/write | 0x0 | Execute Arm instruction enable bit: 0 = disabled 1 = enabled. If this bit is set and an ITR write succeeds, the processor fetches an instruction from the ITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable. |
| UDCCdis | 12 | rwNormal read/write | 0x0 | CP14 debug user access disable control bit: 0 = CP14 debug user access enable 1 = CP14 debug user access disable. If this bit is set and a User mode process attemptsto access any CP14 debug registers, an Undefined Instruction exception is taken. |
| IntDis | 11 | rwNormal read/write | 0x0 | Interrupts disable bit: 0 = interrupts enabled 1 = interrupts disabled. If this bit is set, the nIRQmand nFIQminput signals are inhibited. The external debugger can optionally use this bit to execute pieces of code in normal state aspart of the debugging process and avoid having an interrupt taking control of the program flow. |
| DbgAck | 10 | rwNormal read/write | 0x0 | Force Debug Acknowledge bit. If this bit is set to 1, the DBGACKm output signal is forced HIGH, regardless of the processor state. The external debugger can optionally use this bit to execute pieces of code in normal state as part of the debugging process for the system to behave as if the processor is in debug state. Some systems rely on DBGACKm to determine whether data accesses are application or debugger generated. |
| UND_I | 8 | roRead-only | 0x0 | Sticky Undefined bit: 0 = no Undefined Instruction exception occurred in debug state since the last time this bit was cleared 1 = an Undefined Instruction exception occurred while in debug state since the last time this bit was cleared. This flag detects Undefined Instruction exceptions generated by instructions issued to the processor through the ITR. This bit is set to 1 when anUndefined Instruction exception occurs while the processor is in debug state and is cleared by writing a 1 to DRCR[2]. |
| ADABORT_I | 7 | roRead-only | 0x0 | Sticky asynchronous Data Abort bit: 0 = no asynchronous Data Aborts occurred since the last time this bit was cleared 1 = an asynchronous Data Abort occurred since the last time this bit was cleared. This flag detects asynchronous DataAborts triggered by instructions issued to the processor through the ITR. This bit is set to 1 when an asynchronous Data Abort occurs while the processor is in debug state and is cleared by writing a 1 to DRCR[2]. |
| SDABORT_I | 6 | roRead-only | 0x0 | Sticky synchronous Data Abort bit: 0 = no synchronous Data Abort occurred since the last time this bit was cleared 1 = a synchronous Data Abort occurred since the last time this bit was cleared. This flag detects synchronous DataAborts generated by instructionsissued to the processor through the ITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state and is cleared by writing to the DRCR[2]. |
| MOE | 5:2 | rwNormal read/write | 0x0 | Method of entry bits: 0000 = a DRCR[0] halting debug event occurred 0001 = a breakpoint occurred 0100 = an EDBGRQm halting debug event occurred 0011 = a BKPT instruction occurred 1010 = a synchronous watchpoint occurred others = reserved. These bits are set toindicate any of: . the cause of a debug exception . the cause for entering debug state. A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to determine whether a debug exception occurred and then use these bits to determine the specific debug event. |
| RESTARTED | 1 | roRead-only | 0x1 | CPU restarted bit: 0 = The processor is exiting debug state. 1 = The processor has exited debug state. The debugger can poll this bit to determine when the processor responds to a request to leave debug state. |
| HALTED | 0 | roRead-only | 0x0 | CPU halted bit: 0 = The processor is in normal state. 1 = The processor is in debug state. The debugger can poll this bit to determine when the processor has entered debug state. |