DSGCR (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

DSGCR (DDR_PHY) Register Description

Register Name	DSGCR
Offset Address	0x0000000090
Absolute Address	0x00FD080090 (DDR_PHY)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x02A04101
Description	DDR System General Configuration Register

DSGCR (DDR_PHY) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:28	roRead-only	0x0	Reserved. Return zeroes on reads.
RDBICLSEL	27	rwNormal read/write	0x0	When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1, calculation will use RDBICL, otherwise use default calculation.
RDBICL	26:24	rwNormal read/write	0x2	When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value
PHYZUEN	23	rwNormal read/write	0x1	PHY Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY should also perform impedance calibration (update) whenever there is a DFI update request from the PHY.
Reserved	22	roRead-only	0x0	Reserved. Return zeroes on reads.
RSTOE	21	rwNormal read/write	0x1	SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin.
SDRMODE	20:19	rwNormal read/write	0x0	Single Data Rate Mode: Indicates if the controller or the PHY is configured to run in single data rate (SDR) mode. The default is both the controller and the PHY running in half data rate (HDR) mode. Valid values are: 2b00 = SDR mode if off. Both controller and PHY run in HDR mode 2b01 = Controller runs in SDR mode; PHY runs in HDR mode 2b10 - 2b11 = Reserved
Reserved	18	roRead-only	0x0	Reserved. Return zeroes on reads.
ATOAE	17	rwNormal read/write	0x0	ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O.
DTOOE	16	rwNormal read/write	0x0	DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins.
DTOIOM	15	rwNormal read/write	0x0	DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins.
DTOPDR	14	rwNormal read/write	0x1	DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins.
Reserved	13	roRead-only	0x0	Reserved. Return zeroes on reads.
DTOODT	12	rwNormal read/write	0x0	DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins.
PUAD	11:6	rwNormal read/write	0x4	PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. Note: PUAD should be set to ceiling (10 ns / [ctl_clk period] ) when DSGCR.CTLZUEN or DSGCR.PHYZUEN are set 1`b1. Otherwise it can be programmed to 0. In LPDDR4 if incremental DQS2DQ WEYE is enabled, PUAD should be set to ceiling ((tZQLAT/2) / [ctl_clk period]).
CUAEN	5	rwNormal read/write	0x0	Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update.
Reserved	4:3	roRead-only	0x0	Reserved. Return zeroes on reads.
CTLZUEN	2	rwNormal read/write	0x0	Controller Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY should also perform impedance calibration (update) whenever there is a DFI update request.
Reserved	1	roRead-only	0x0	Reserved. Return zeroes on reads.
PUREN	0	rwNormal read/write	0x1	PHY Update Request Enable: Specifies if set, that the PHY should issue PHY-initiated update request when there is DDL VT drift.