DTAR0 (DDR_PHY) Register Description
Register Name | DTAR0 |
---|---|
Offset Address | 0x0000000208 |
Absolute Address | 0x00FD080208 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x04000000 |
Description | Data Training Address Register 0 |
DTAR0 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:30 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
MPRLOC | 29:28 | rwNormal read/write | 0x0 | Multi-Purpose Register (MPR) Location: Selects MPR data location to use as a training pattern during gate training. Valid values are: 2b00 = Serial 2b01 = Parallel (DDR4 only) 2b10 = Staggered (DDR4 only) 2b11 = Reserved |
DTBGBK1 | 27:24 | rwNormal read/write | 0x4 | Data Training Bank Group and Bank Address: Selects the SDRAM bank group and bank address to be used during data training in DDR4 mode only. When in DDR4 mode, DTBGBK1[25:24] specifies the bank group and DTBGBK1[27:26] specifies the bank address. When not in DDR4 mode, DTBGBK1 is not applicable. |
DTBGBK0 | 23:20 | rwNormal read/write | 0x0 | Data Training Bank Group and Bank Address: Selects the SDRAM bank group and bank address to be used during data training. When in DDR4 mode, DTBGBK0[23:22] specifies the bank group and DTBGBK0[21:20] specifies the bank address. When not in DDR4 mode DTBGBK0[22:20] specify the bank address. |
Reserved | 19:18 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
DTROW | 17:0 | rwNormal read/write | 0x0 | Data Training Row Address: Selects the SDRAM row address to be used during data training. |