DTAR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DTAR0 (DDR_PHY) Register Description

Register NameDTAR0
Offset Address0x0000000208
Absolute Address 0x00FD080208 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x04000000
DescriptionData Training Address Register 0

DTAR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Reserved. Return zeros on reads.
MPRLOC29:28rwNormal read/write0x0Multi-Purpose Register (MPR) Location: Selects MPR data location to
use as a training pattern during gate training. Valid values are:
2b00 = Serial
2b01 = Parallel (DDR4 only)
2b10 = Staggered (DDR4 only)
2b11 = Reserved
DTBGBK127:24rwNormal read/write0x4Data Training Bank Group and Bank Address: Selects the SDRAM
bank group and bank address to be used during data training in DDR4
mode only.
When in DDR4 mode, DTBGBK1[25:24] specifies the bank group and
DTBGBK1[27:26] specifies the bank address.
When not in DDR4 mode, DTBGBK1 is not applicable.
DTBGBK023:20rwNormal read/write0x0Data Training Bank Group and Bank Address: Selects the SDRAM
bank group and bank address to be used during data training.
When in DDR4 mode, DTBGBK0[23:22] specifies the bank group and
DTBGBK0[21:20] specifies the bank address.
When not in DDR4 mode DTBGBK0[22:20] specify the bank address.
Reserved19:18roRead-only0x0Reserved. Return zeros on reads.
DTROW17:0rwNormal read/write0x0Data Training Row Address: Selects the SDRAM row address to be
used during data training.