DTAR1 (DDR_PHY) Register Description
| Register Name | DTAR1 |
|---|---|
| Offset Address | 0x000000020C |
| Absolute Address | 0x00FD08020C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00010000 |
| Description | Data Training Address Register 1 |
DTAR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| DTCOL1 | 24:16 | rwNormal read/write | 0x1 | Data Training Column Address: Selects the SDRAM column address to be used during data training. Specified in multiples of 8, such that the address used is {DTCOL1,3'b000}. For LPDDR4 systems, specified in multiples of 16, such that the address used is {DTCOL1,4'b0000}. |
| Reserved | 15:9 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| DTCOL0 | 8:0 | rwNormal read/write | 0x0 | Data Training Column Address: Selects the SDRAM column address to be used during data training. Specified in multiples of 8, such that the address used is {DTCOL0,3'b000}. For LPDDR4 systems, specified in multiples of 16, such that the address used is {DTCOL0,4'b0000}. |