DTAR2 (DDR_PHY) Register Description
| Register Name | DTAR2 |
|---|---|
| Offset Address | 0x0000000210 |
| Absolute Address | 0x00FD080210 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00030002 |
| Description | Data Training Address Register 2 |
DTAR2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| DTCOL3 | 24:16 | rwNormal read/write | 0x3 | Data Training Column Address: Selects the SDRAM column address to be used during data training. Specified in multiples of 8, such that the address used is {DTCOL3,3'b000}. For LPDDR4 systems, specified in multiples of 16, such that the address used is {DTCOL3,4'b0000}. |
| Reserved | 15:9 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| DTCOL2 | 8:0 | rwNormal read/write | 0x2 | Data Training Column Address: Selects the SDRAM column address to be used during data training. Specified in multiples of 8, such that the address used is {DTCOL2,3'b000}. For LPDDR4 systems, specified in multiples of 16, such that the address used is {DTCOL2,4'b0000}. |