DTCR0 (DDR_PHY) Register Description
| Register Name | DTCR0 |
|---|---|
| Offset Address | 0x0000000200 |
| Absolute Address | 0x00FD080200 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x800091C7 |
| Description | Data Training Configuration Register 0 |
DTCR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| RFSHDT | 31:28 | rwNormal read/write | 0x8 | Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. |
| Reserved | 27:26 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| DTDRS | 25:24 | rwNormal read/write | 0x0 | Data Training Debug Rank Select: Selects the rank during training debug mode. |
| DTEXG | 23 | rwNormal read/write | 0x0 | Data Training with Early/Extended Gate: Specifies if set that the DQS gate training should be performed with an early/extended gate as specified in DXSL*DQSCTL.DQSGX. |
| DTEXD | 22 | rwNormal read/write | 0x0 | Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes. Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment. |
| DTDSTP | 21 | wtcReadable, write a 1 to clear | 0x0 | Data Training Debug Step: A write of '1' to this bit steps the data training algorithm through a single step. This bit is self clearing. |
| DTDEN | 20 | rwNormal read/write | 0x0 | Data Training Debug Enable: Enables, if set, the data training to run in a single-step debug mode. In this mode, DTDSTP must be repeatedly asserted to step through the data training. |
| DTDBS | 19:16 | rwNormal read/write | 0x0 | Data Training Debug Byte Select: Selects the byte during data training debug mode. |
| DTRDBITR | 15:14 | rwNormal read/write | 0x2 | Data Training read DBI deskewing configuration. Configures the data training read bit deskewing algorithm optional RDBI deskew functionality. Valid values are: 2'b00, 2'b10 = RDBI deskewing is not performed 2'b01 = RDBI deskewing is performed. If during RDBI deskewing, the RDBI BDL is exhausted, the RDBI deskewing algorithm exits and the normal deskewing algorithm continues 2'b11 = RDBI deskewing is performed. If during RDBI deskewing the RDBI BDL is exhausted, the RDBI deskewing algorithm proceeds by moving the RDQS LCDL and RDQ BDLs instead |
| Reserved | 13 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| DTWBDDM | 12 | rwNormal read/write | 0x1 | Data Training Write Bit Deskew Data Mask. If set it enables write bit deskew of the data mask. |
| RFSHEN | 11:8 | rwNormal read/write | 0x1 | Refreshes Issued During Entry to Training: |
| DTCMPD | 7 | rwNormal read/write | 0x1 | Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data- training only checks if the correct number of DQS edges were returned. |
| DTMPR | 6 | rwNormal read/write | 0x1 | Data Training Using MPR: Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back. Notes: * DDR4 and DDR3 only * For initial training, this bit must be set to 1. Prior to write data training, writes to memory may not be successful Caution: The value 0x0 is not supported for this field |
| Reserved | 5 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| INCWEYE | 4 | rwNormal read/write | 0x0 | Incremental WEYE Training using MPC FIFO Commands: This is applicable in LPDDR4 mode. When this bit is set to 1, incremental WEYE training is performed with MPC FIFO commands instead of normal Writes/Reads when controller issues dfi_ctrlupd_req. This Incremental WEYE training computes new Min and Max for each rank on each separate dfi_ctrlupd_req. Note: The WDLVT bit in the 'DATX8 General Configuration Register 3 (DXnGCR3)' register must be set 0 when INCWEYE bit is set 1. |
| DTRPTN | 3:0 | rwNormal read/write | 0x7 | Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read. The valid values are 1 to 15. |