DTDR1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DTDR1 (DDR_PHY) Register Description

Register NameDTDR1
Offset Address0x000000021C
Absolute Address 0x00FD08021C (DDR_PHY)
Width32
TyperwNormal read/write
Reset Value0x7788BB44
DescriptionData Training Data Register 1

DTDR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DTBYTE731:24rwNormal read/write0x77Data Training Data
DTBYTE623:16rwNormal read/write0x88Data Training Data
DTBYTE515:8rwNormal read/write0xBBData Training Data
DTBYTE4 7:0rwNormal read/write0x44Data Training Data: The second 4 bytes of data used during data
training. This same data byte is used for each Byte Lane. Default
sequence is a walking 1 while toggling data every data cycle.