DTPR1 (DDR_PHY) Register Description
| Register Name | DTPR1 |
|---|---|
| Offset Address | 0x0000000114 |
| Absolute Address | 0x00FD080114 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x5656041E |
| Description | DRAM Timing Parameters Register 1 |
DTPR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tWLMRD | 30:24 | rwNormal read/write | 0x56 | Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. Larger values give more conservative command-to-command timings |
| Reserved | 23 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tFAW | 22:16 | rwNormal read/write | 0x56 | 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 127. Larger values give more conservative command-to- command timings |
| Reserved | 15:11 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |
| tMOD | 10:8 | rwNormal read/write | 0x4 | Load mode update delay (DDR4 and DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values for DDR4 are: 3b000 = 24 3b001 = 25 3b010 = 26 3b011 = 27 3b100 = 28 3b101 = 29 3b110 = 30 3b111 = 30 Valid values for DDR3 are: 3b000 = 12 3b001 = 13 3b010 = 14 3b011 = 15 3b100 = 16 3b101 = 17 3b110 - 3b111 = 17 Note: This field should be left at default value for LPDDR3 and LPDDR4. |
| Reserved | 7:5 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tMRD | 4:0 | rwNormal read/write | 0x1E | Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. An offset is applied in some DRAM modes to extend the range of the register as follows: DDR3: +4 is added to register LPDDR3 and DDR4: +8 is added to register, and LPDDR4: no offset is applied (+0 add to register) Larger values give more conservative command-to-command timings. |