DTPR2 (DDR_PHY) Register Description
| Register Name | DTPR2 |
|---|---|
| Offset Address | 0x0000000118 |
| Absolute Address | 0x00FD080118 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x000B01D0 |
| Description | DRAM Timing Parameters Register 2 |
DTPR2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:29 | roRead-only | 0x0 | Return zeroes on reads. |
| tRTW | 28 | rwNormal read/write | 0x0 | Read to Write command delay. Valid values are: 0 = standard bus turn around delay 1 = add 1 clock to standard bus turn around delay This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. |
| Reserved | 27:25 | roRead-only | 0x0 | Return zeroes on reads. |
| tRTODT | 24 | rwNormal read/write | 0x0 | Read to ODT delay. Setting to 1 increases read-to-write transaction spacing by 1 DRAM clock cycle. This is intended a programmable margin for host ODT turn-off timing. |
| Reserved | 23:20 | roRead-only | 0x0 | Return zeroes on reads. |
| tCKE | 19:16 | rwNormal read/write | 0xB | CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 and LPDDR3, this parameter must be set to the value of tCKESR, which is usually bigger than the value of tCKE. Valid values are 2 to 15. Larger values give more conservative command-to-command timings. |
| Reserved | 15:10 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tXS | 9:0 | rwNormal read/write | 0x1D0 | Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXS, tXSDLL) for DDR3 and DDR4. Valid values are 2 to 1023. For LPDDR3 and LPDDR4 mode, program this value to set tXSR, as specified in the SDRAM datasheet. Larger values give more conservative command-to-command timings. |