DTPR3 (DDR_PHY) Register Description
| Register Name | DTPR3 |
|---|---|
| Offset Address | 0x000000011C |
| Absolute Address | 0x00FD08011C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x02000804 |
| Description | DRAM Timing Parameters Register 3 |
DTPR3 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| tOFDx | 31:29 | rwNormal read/write | 0x0 | ODT turn-off delay extension. The delays are in clock cycles. Valid values are: 000 = 0 001 = 1 010 = 2 011 = 3 100 = 4 101 = 5 110 = 6 111 = 7 Delays ODT turnoff by Extending ODT on time by 0-7 cycles for all PUB-initiated transactions |
| tCCD | 28:26 | rwNormal read/write | 0x0 | Read to read and write to write command delay. In DDR4 mode of operation this field is not used, MR6.tCCDL is used instead. Valid values are: 3b000 = BL/2 3b001 = BL/2 + 1 3b010 - 3b111 = Reserved |
| tDLLK | 25:16 | rwNormal read/write | 0x200 | DLL locking time. The PUB adds an offset of 128 to this programmed register value to derive the final tDLLK value. Valid values are 0 to 1023, giving valid tDLLK values of 128 to 1151. Default value gives tDLLK value of 512. |
| Reserved | 15:12 | roRead-only | 0x0 | Return zeroes on reads. |
| tDQSCKmax | 11:8 | rwNormal read/write | 0x8 | Maximum DQS output access time from CK/CK# (LPDDR3/4 only). This value is used for implementing read-to-write spacing. Valid values are 1 to 8. Programming larger values increase read-to-write timing margins; smaller values optimize read-to-write scheduling (provided protocol requirements are still met). |
| Reserved | 7:3 | roRead-only | 0x0 | Return zeroes on reads. |
| TDQSCK | 2:0 | rwNormal read/write | 0x4 | DQS output access time from CK/CK# (LPDDR3/4 only). This value is used for computing the read latency. Valid values are 1 to 7. * For LPDDR3 operation with gate extension and gate training disabled, for operation at or above 2000 Mbps, set this to 4. * For LPDDR3 operation with gate extension and gate training disabled, for operation below 2000 Mbps, set this to (tDQSCKmin/tCK) + 1, rounding down to the nearest whole number. * For LPDDR3 or LPDDR4 operation with gate training enabled, for operation at or above1600 Mbps, set this to (tDQSCKmin/tCK) rounded down to the nearest whole number. * For LPDDR3 or LPDDR4 operation with gate training enabled, for operation below 1600 Mbps, set this to 1. * Set to 0 for DDR3 or DDR4 operation. tCK is the DRAM clock period. See DRAM device specification for values of tDQSCKmin. |