DTPR4 (DDR_PHY) Register Description
| Register Name | DTPR4 |
|---|---|
| Offset Address | 0x0000000120 |
| Absolute Address | 0x00FD080120 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x01C02B10 |
| Description | DRAM Timing Parameters Register 4 |
DTPR4 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | roRead-only | 0x0 | Return zeroes on reads. |
| tAOND_tAOFD | 29:28 | rwNormal read/write | 0x0 | ODT turn-on/turn-off delays. The delays are in clock cycles. Valid values are: 2b00 = 2/2.5 2b01 = 3/3.5 2b10 = 4/4.5 2b11 = 5/5.5 |
| Reserved | 27:26 | roRead-only | 0x0 | Return zeroes on reads. |
| tRFC | 25:16 | rwNormal read/write | 0x1C0 | Refresh-to-Refresh: Indicates the minimum time, in clock cycles, between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min) parameter value supported. Larger values give more conservative command-to-command timings. |
| Reserved | 15:14 | roRead-only | 0x0 | Return zeroes on reads. |
| tWLO | 13:8 | rwNormal read/write | 0x2B | Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. Larger values give more conservative command-to-command timings. |
| Reserved | 7:5 | roRead-only | 0x0 | Return zeroes on reads. |
| tXP | 4:0 | rwNormal read/write | 0x10 | Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXPDLL) for DDR3. For DDR4 and LPDDR3, set this to tXP as specified in the SDRAM data sheet. Valid values are 2 to 31. For LPDDR4 mode, program this value to tXP as specified in the SDRAM datasheet. This register field is also used for tCKEHCS - Valid CS Requirement after CKE Input High timing parameter in LPDDR4 mode Note: For LPDDR4, additional offset of +3 tCK must be added to the value calculated for the corresponding speed grade. Larger values give more conservative command-to-command timings. |