DTPR5 (DDR_PHY) Register Description
| Register Name | DTPR5 |
|---|---|
| Offset Address | 0x0000000124 |
| Absolute Address | 0x00FD080124 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00872716 |
| Description | DRAM Timing Parameters Register 5 |
DTPR5 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tRC | 23:16 | rwNormal read/write | 0x87 | Activate to activate command delay (same bank). Valid values are 2 to 255. |
| Reserved | 15 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tRCD | 14:8 | rwNormal read/write | 0x27 | Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. In LPDDR3 mode, use tRCD(slow) - max(24ns,3nCK) to set this parameter. Also, PUB adds an offset of 8 to the register value. In DDR3, DDR4, and LPDDR4 modes, no offset is added. Larger values give more conservative command-to-command timings. |
| Reserved | 7:5 | roRead-only | 0x0 | Return zeroes on reads. |
| tWTR | 4:0 | rwNormal read/write | 0x16 | DRAM Internal write to read command delay. For DDR4, use tWTR_L (write-to-read delay for same bank group). Larger values give more conservative command-to-command timings. |