DTPR6 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DTPR6 (DDR_PHY) Register Description

Register NameDTPR6
Offset Address0x0000000128
Absolute Address 0x00FD080128 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000505
DescriptionDRAM Timing Parameters Register 6

DTPR6 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PUBWLEN31rwNormal read/write0x0PUB Write Latency Enable: Specifies, if set, that the PUB should use
the write latency specified in DTPR6.PUBWL. Otherwise, if not set, the
PUB write latency is automatically calculated from the mode register
settings.
PUBRLEN30rwNormal read/write0x0PUB Read Latency Enable: Specifies, if set, that the PUB should use
the read latency specified in DTPR6.PUBRL. Otherwise, if not set, the
PUB read latency is automatically calculated from the mode register
settings.
Reserved29:14roRead-only0x0Return zeroes on reads.
PUBWL13:8rwNormal read/write0x5Write Latency: Specifies the write latency that should be used inside the
PUB when DTPTR6.PUBWL is set to 1. Valid values are 1 to 31. If
PUBWLEN is not set, then the PUB write latency is automatically
calculated from the mode register settings.
Reserved 7:6roRead-only0x0Return zeroes on reads.
PUBRL 5:0rwNormal read/write0x5Read Latency: Specifies the read latency that should be used inside the
PUB when DTPTR6.PUBRLEN is set to 1. Valid values are 1 to 31. If
PUBRL is not set, then the PUB read latency is automatically calculated
from the mode register settings.