DX0BDLR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX0BDLR0 (DDR_PHY) Register Description

Register NameDX0BDLR0
Offset Address0x0000000740
Absolute Address 0x00FD080740 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Bit Delay Line Register 0

DX0BDLR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Return zeroes on reads.
DQ3WBD29:24rwNormal read/write0x0DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path
Reserved23:22roRead-only0x0Return zeroes on reads.
DQ2WBD21:16rwNormal read/write0x0DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path.
Reserved15:14roRead-only0x0Return zeroes on reads.
DQ1WBD13:8rwNormal read/write0x0DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path.
Reserved 7:6roRead-only0x0Return zeroes on reads.
DQ0WBD 5:0rwNormal read/write0x0DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path.