DX0GCR1 (DDR_PHY) Register Description
Register Name | DX0GCR1 |
---|---|
Offset Address | 0x0000000704 |
Absolute Address | 0x00FD080704 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00007FFF |
Description | DATX8 n General Configuration Register 1 |
DX0GCR1 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DXPDRMODE | 31:16 | rwNormal read/write | 0x0 | Enables the PDR mode values for DQ[7:0]. The bit [1:0] is for DQ[0], bit[3:2] for DQ[1] etc. Valid values are: 2b00 = PDR Dynamic 2b01 = PDR always ON 2b10 = PDR always OFF 2b11 = Reserved |
Reserved | 15 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
QSNSEL | 14 | rwNormal read/write | 0x1 | Selects the delayed or non-delayed dead data strobe # 1'b0: Selects delayed read data strobe 1'b1: Selects non-delayed read data strobe# |
QSSEL | 13 | rwNormal read/write | 0x1 | Selects the delayed or non-delayed dead data strobe 1'b0: Selects delayed read data strobe 1'b1: Selects non-delayed read data strobe |
OEEN | 12 | rwNormal read/write | 0x1 | Output Enable Clock Gate: When set to 0, this signal will gate (stop) the clocks to all registers inside the I/O output enable (D) slice. |
PDREN | 11 | rwNormal read/write | 0x1 | I/O Power-Down Receiver Clock Gate: When set to 0, this signal will gate (stop) the clocks to all registers inside the I/O power-down receiver (D) slice. |
TEEN | 10 | rwNormal read/write | 0x1 | I/O Terminate Enable Clock Gate: When set to 0, this signal will gate (stop) the clocks to all registers inside the I/O terminate enable (D) slice. |
DSEN | 9 | rwNormal read/write | 0x1 | Data Strobe, Data Strobe #, Read Data Valid, Read Data Strobe, Read Data Strobe Gate, Control Clock Gate and Clock Generator Clock Gate: When set to 0, this signal will gate (stop) the clocks to all registers inside the corresponding block. Read Data Strobe, Read Data Strobe#, Read Data Strobe gate Enable: Enables, when set to 1. |
DMEN | 8 | rwNormal read/write | 0x1 | Data Mask Clock Gate: When set to 0, this signal will gate (stop) the clock to all registers inside a correspondingly numbered data output (D) slice. Read Data Mask Clock Gate: When set to 0, this signal will gate (stop) the clock to all registers inside a correspondingly numbered read data input (Q) slice. Read Data Mask Enable: Enables, if set to 1, the read data path. |
DQEN | 7:0 | rwNormal read/write | 0xFF | Enables DQ corresponding to each bit in a byte Data Clock Gate: When set to 0, this signal will gate (stop) the clock to all registers inside a correspondingly numbered data output (D) slice. Read Data Clock Gate: When set to 0, this signal will gate (stop) the clock to all registers inside a correspondingly numbered read data input (Q) slice. Read Data Enable: Enables, if set to 1, the read data path. Notes: 1. Byte #0 must always be enabled. 2. In LPDDR4 both the bytes of channel should be enabled or disabled together to support DQS2DQ training and CBT Training. 3. In LPDDR3, the lower 16 bits should be enabled or disabled together to support the CA training. |