DX0GCR4 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX0GCR4 (DDR_PHY) Register Description

Register NameDX0GCR4
Offset Address0x0000000710
Absolute Address 0x00FD080710 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0200003C
DescriptionDATX8 n General Configuration Register 4

DX0GCR4 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29roRead-only0x0Reserved. Returns zeros on reads.
DXREFPEN28rwNormal read/write0x0Byte Lane VREF Pad Enable: Enables the pass gate between (to
connect) VREF and PAD.
DXREFSEN25rwNormal read/write0x1Byte Lane Single-End VREF Enable: Enables the generation of
VREF value for internal byte lane single-end IO buffers.
Reserved24roRead-only0x0Reserved. Returns zeros on reads.
DXREFSSELRANGE15rwNormal read/write0x0Single ended VREF generator REFSEL range select
DXREFSSEL14:8rwNormal read/write0x0Byte Lane Single-End VREF Select: Selects the generated VREF
value for internal byte lane single-end I/O buffers.
Reserved 7:6roRead-only0x0Reserved. Returns zeros on reads.
DXREFIEN 5:2rwNormal read/write0xFVREF Enable control for DQ IO (Single Ended) buffers of a byte
lane.
DXREFIMON 1:0rwNormal read/write0x0VRMON control for DQ IO (Single Ended) buffers of a byte lane.