DX0MDLR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX0MDLR0 (DDR_PHY) Register Description

Register NameDX0MDLR0
Offset Address0x00000007A0
Absolute Address 0x00FD0807A0 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Master Delay Line Register 0

DX0MDLR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Return zeroes on reads.
TPRD24:16rwNormal read/write0x0Target Period: Target period measured by the master delay line
calibration for VT drift compensation. This is the current measured
value of the period and is continuously updated if the MDL is enabled
to do so.
Reserved15:9roRead-only0x0Return zeroes on reads.
IPRD 8:0rwNormal read/write0x0Initial Period: Initial period measured by the master delay line
calibration for VT drift compensation. This value is used as the
denominator when calculating the ratios of updates during VT
compensation.