DX0MDLR1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX0MDLR1 (DDR_PHY) Register Description

Register NameDX0MDLR1
Offset Address0x00000007A4
Absolute Address 0x00FD0807A4 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Master Delay Line Register 1

DX0MDLR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9roRead-only0x0Reserved. Return zeroes on reads.
MDLD 8:0rwNormal read/write0x0MDL Delay: Delay select for the LCDL for the Master Delay Line.