DX1LCDLR1 (DDR_PHY) Register Description
Register Name | DX1LCDLR1 |
---|---|
Offset Address | 0x0000000884 |
Absolute Address | 0x00FD080884 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | DATX8 n Local Calibrated Delay Line Register 1 |
DX1LCDLR1 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | roRead-only | 0x0 | Return zeroes on reads. |
Reserved | 24:16 | roRead-only | 0x0 | Returns zeroes on reads. Caution: Do not write to this register field. |
Reserved | 15:9 | roRead-only | 0x0 | Return zeroes on reads. |
WDQD | 8:0 | rwNormal read/write | 0x0 | Write Data Delay: Delay select for the write data (WDQ) LCDL for the byte. The WDQ LCDL register is automatically updated after DDL Calibration (by Tck/4) and after Write leveling when write leveling is performed. Total delay should be written into this field. It overrides the delay set by hardware. Delay written in this field is converted to following two elements after 20 ctl_clk clock cycles: 1-Number of UI delays (pipelines) added to write dq path that can be read from DxnGTR0.WDQSL field 2-The remainder of the delay, which is number of LCDL tap delays (written delay - DxnGTR0.WDQSL * one UI period). It is smaller than 1 UI delay and will be available to read in this field. Reading this field returns the delay in item 2. This field should be programmed only after running calibration. |