DX2BDLR6 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX2BDLR6 (DDR_PHY) Register Description

Register NameDX2BDLR6
Offset Address0x0000000960
Absolute Address 0x00FD080960 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Bit Delay Line Register 6

DX2BDLR6 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:22roRead-only0x0Return zeroes on reads.
TERBD21:16rwNormal read/write0x0Termination Enable Bit Delay: Delay select for the BDL.
Reserved15:14roRead-only0x0Return zeroes on reads.
PDRBD13:8rwNormal read/write0x0Power down receiver Bit Delay: Delay select for the BDL.
Reserved 7:0roRead-only0x0Return zeroes on reads.