DX2GCR3 (DDR_PHY) Register Description
| Register Name | DX2GCR3 |
|---|---|
| Offset Address | 0x000000090C |
| Absolute Address | 0x00FD08090C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x3F000008 |
| Description | DATX8 n General Configuration Register 3 |
DX2GCR3 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
| RDBVT | 29 | rwNormal read/write | 0x1 | Read Data BDL VT Compensation: Enables, if set the VT drift compensation of the read data bit delay lines. |
| WDBVT | 28 | rwNormal read/write | 0x1 | Write Data BDL VT Compensation: Enables, if set the VT drift compensation of the write data bit delay lines. |
| RGLVT | 27 | rwNormal read/write | 0x1 | Read DQS Gating LCDL Delay VT Compensation: Enables, if set the VT drift compensation of the read DQS gating LCDL. |
| RDLVT | 26 | rwNormal read/write | 0x1 | Read DQS LCDL Delay VT Compensation: Enables, if set the VT drift compensation of the read DQS LCDL. |
| WDLVT | 25 | rwNormal read/write | 0x1 | Write DQ LCDL Delay VT Compensation: Enables, if set the VT drift compensation of the write DQ LCDL. Note: WDLVT register must be set 0 when the INCWEYE bit is set 1 in the 'Data Training Configuration Register 0 (DTCR0)'. |
| WLLVT | 24 | rwNormal read/write | 0x1 | Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL. |
| Reserved | 23:22 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
| DSNOEMODE | 21:20 | rwNormal read/write | 0x0 | Enables the OE mode values for DQS. Valid values are: 2b00 = OE Dynamic 2b01 = OE always ON 2b10 = OE always OFF 2b11 = Reserved |
| DSNTEMODE | 19:18 | rwNormal read/write | 0x0 | Enables the TE mode values for DQS. Valid values are: 2b00 = TE (ODT) Dynamic 2b01 = TE (ODT) always ON 2b10 = TE (ODT) always OFF 2b11 = Reserved |
| DSNPDRMODE | 17:16 | rwNormal read/write | 0x0 | Enables the PDR mode values for DQS. Valid values are: 2b00 = PDR Dynamic 2b01 = PDR always ON 2b10 = PDR always OFF 2b11 = Reserved |
| DMOEMODE | 15:14 | rwNormal read/write | 0x0 | Enables the OE mode values for DM. Valid values are: 2b00 = OE Dynamic 2b01 = OE always ON 2b10 = OE always OFF 2b11 = Reserved |
| DMTEMODE | 13:12 | rwNormal read/write | 0x0 | Enables the TE mode values for DM. Valid values are: 2b00 = TE (ODT) Dynamic 2b01 = TE (ODT) always ON 2b10 = TE (ODT) always OFF 2b11 = Reserved |
| DMPDRMODE | 11:10 | rwNormal read/write | 0x0 | Enables the PDR mode values for DM. Valid values are: 2b00 = PDR Dynamic 2b01 = PDR always ON 2b10 = PDR always OFF 2b11 = Reserved |
| Reserved | 9:8 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
| DSOEMODE | 7:6 | rwNormal read/write | 0x0 | Enables the OE mode values for DQS. Valid values are: 2b00 = OE Dynamic 2b01 = OE always ON 2b10 = OE always OFF 2b11 = Reserved |
| DSTEMODE | 5:4 | rwNormal read/write | 0x0 | Enables the TE mode values for DQS. Valid values are: 2b00 = TE (ODT) Dynamic 2b01 = TE (ODT) always ON 2b10 = TE (ODT) always OFF 2b11 = Reserved |
| DSPDRMODE | 3:2 | rwNormal read/write | 0x2 | Enables the PDR mode values for DQS. Valid values are: 2b00 = PDR Dynamic 2b01 = PDR always ON 2b10 = PDR always OFF 2b11 = Reserved |
| Reserved | 1:0 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |