DX2GTR0 (DDR_PHY) Register Description
Register Name | DX2GTR0 |
---|---|
Offset Address | 0x00000009C0 |
Absolute Address | 0x00FD0809C0 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00020000 |
Description | DATX8 n General Timing Register 0 |
DX2GTR0 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:27 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
WDQSL | 26:24 | rwNormal read/write | 0x0 | DQ write path latency pipeline: Write data is pipelined by (WLSL + WDQSL). Total write data pipeline is: [Write leveling system latency] + WDQSL/2 DRAM clock periods. This value is adjusted by LPDDR4 tDQS2DQ training and write eye centering. Any update to DXnLCDLR1.WDQD updates this field after 20 ctl_clk clock cycles. Reading this field shows the number of pipelines (UI delays) written into DXnLCDLR1.WDQD field. Ensure this field is never overwritten by SW. Writing into this field changes (corrupts) the total write DQ delay written into DXnLCDLR1.WDQD field. |
Reserved | 23:20 | roRead-only | 0x0 | Reserved. Caution, do not write to this register field. |
WLSL | 19:16 | rwNormal read/write | 0x2 | Write Leveling System Latency: Used to adjust the write latency after write leveling. This field is for the byte when in x8 mode Valid values: 0000 = Write latency = WL - 1 0001 = Write latency = WL - 0.5 0010 = Write latency = WL 0011 = Write latency = WL + 0.5 0100 = Write latency = WL + 1 0101 = Write latency = WL + 1.5 0110 = Write latency = WL + 2 0111 = Write latency = WL + 2.5 1000 = Write latency = WL + 3 1001 = Write latency = WL + 3.5 1010 = Write latency = WL + 4 1011 - 1111 = RESERVED |
Reserved | 15:13 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
Reserved | 12:8 | roRead-only | 0x0 | Reserved. Caution, do not write to this register field. |
Reserved | 7:5 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
DGSL | 4:0 | rwNormal read/write | 0x0 | DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data. This is used to compensate for board delays and other system delays. Power-up default is 0x00 (i.e. no extra clock cycles required). Valid values are 0 to 18 and each increment adds a half SDRAM CK period. Note: This field is for the byte when in x8 mode |