DX2GTR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX2GTR0 (DDR_PHY) Register Description

Register NameDX2GTR0
Offset Address0x00000009C0
Absolute Address 0x00FD0809C0 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00020000
DescriptionDATX8 n General Timing Register 0

DX2GTR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:27roRead-only0x0Reserved. Return zeroes on reads.
WDQSL26:24rwNormal read/write0x0DQ write path latency pipeline: Write data is pipelined by (WLSL +
WDQSL). Total write data pipeline is:
[Write leveling system latency] + WDQSL/2 DRAM clock periods.
This value is adjusted by LPDDR4 tDQS2DQ training and write
eye centering.
Any update to DXnLCDLR1.WDQD updates this field after 20
ctl_clk clock cycles. Reading this field shows the number of
pipelines (UI delays) written into DXnLCDLR1.WDQD field.
Ensure this field is never overwritten by SW.
Writing into this field changes (corrupts) the total write DQ delay
written into DXnLCDLR1.WDQD field.
Reserved23:20roRead-only0x0Reserved. Caution, do not write to this register field.
WLSL19:16rwNormal read/write0x2Write Leveling System Latency: Used to adjust the write latency
after write leveling. This field is for the byte when in x8 mode
Valid values:
0000 = Write latency = WL - 1
0001 = Write latency = WL - 0.5
0010 = Write latency = WL
0011 = Write latency = WL + 0.5
0100 = Write latency = WL + 1
0101 = Write latency = WL + 1.5
0110 = Write latency = WL + 2
0111 = Write latency = WL + 2.5
1000 = Write latency = WL + 3
1001 = Write latency = WL + 3.5
1010 = Write latency = WL + 4
1011 - 1111 = RESERVED
Reserved15:13roRead-only0x0Reserved. Return zeroes on reads.
Reserved12:8roRead-only0x0Reserved. Caution, do not write to this register field.
Reserved 7:5roRead-only0x0Reserved. Return zeroes on reads.
DGSL 4:0rwNormal read/write0x0DQS Gating System Latency: This is used to increase the number
of clock cycles needed to expect valid DDR read data. This is
used to compensate for board delays and other system delays.
Power-up default is 0x00 (i.e. no extra clock cycles required). Valid
values are 0 to 18 and each increment adds a half SDRAM CK
period.
Note: This field is for the byte when in x8 mode