DX3BDLR2 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX3BDLR2 (DDR_PHY) Register Description

Register NameDX3BDLR2
Offset Address0x0000000A48
Absolute Address 0x00FD080A48 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Bit Delay Line Register 2

DX3BDLR2 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Return zeroes on reads.
DSNWBD29:24rwNormal read/write0x0DQSN Write Bit Delay: Delay select for the BDL on DQSN write path
Reserved23:22roRead-only0x0Return zeroes on reads.
DSOEBD21:16rwNormal read/write0x0DQS/DM/DQ Output Enable Bit Delay: Delay select for the BDL.
Reserved15:14roRead-only0x0Return zeroes on reads.
DSWBD13:8rwNormal read/write0x0DQS Write Bit Delay: Delay select for the BDL on DQS write path
Reserved 7:6roRead-only0x0Return zeroes on reads.
DMWBD 5:0rwNormal read/write0x0DM Write Bit Delay: Delay select for the BDL on DM write path.