DX3BDLR4 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX3BDLR4 (DDR_PHY) Register Description

Register NameDX3BDLR4
Offset Address0x0000000A54
Absolute Address 0x00FD080A54 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Bit Delay Line Register 4

DX3BDLR4 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Return zeroes on reads.
DQ7RBD29:24rwNormal read/write0x0DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path.
Reserved23:22roRead-only0x0Return zeroes on reads.
DQ6RBD21:16rwNormal read/write0x0DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path.
Reserved15:14roRead-only0x0Return zeroes on reads.
DQ5RBD13:8rwNormal read/write0x0DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path.
Reserved 7:6roRead-only0x0Return zeroes on reads.
DQ4RBD 5:0rwNormal read/write0x0DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path.