DX3GSR1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX3GSR1 (DDR_PHY) Register Description

Register NameDX3GSR1
Offset Address0x0000000AE4
Absolute Address 0x00FD080AE4 (DDR_PHY)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDATX8 n General Status Register 1

DX3GSR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Reserved. Returns zeroes on reads.
DLTCODE24:1roRead-only0x0Delay Line Test Code: Returns the code measured by the PHY
control block that corresponds to the period of the DATX8 delay line
digital test output.
DLTDONE 0roRead-only0x0Delay Line Test Done: Indicates, if set, that the PHY control block
has finished doing period measurement of the DATX8 delay line
digital test output.