DX3GSR3 (DDR_PHY) Register Description
| Register Name | DX3GSR3 |
|---|---|
| Offset Address | 0x0000000AEC |
| Absolute Address | 0x00FD080AEC (DDR_PHY) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | DATX8 n General Status Register 3 |
DX3GSR3 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:27 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| ESTAT | 26:24 | roRead-only | 0x0 | VREF Training Error Status Code: Indicates which phase of error check failed. Valid status encodings are: ESTAT[0] = Init vref check failed. ESTAT[1] = Final check for DRAM VREF failed ESTAT[2] = Final check for Host VREF failed. Note: ESTAT Register field is valid only when there is a bit set in DXnGSR3.DVERR or DXnGSR3.HVERR. |
| DVERR | 17:16 | roRead-only | 0x0 | DRAM VREF Training Error: Indicates if set that there was an error in VREF Training. Each bit indicates an error for one rank. |
| HVERR | 9:8 | roRead-only | 0x0 | Host VREF Training Error: Indicates if set that there was an error in VREF Training. Each bit indicates an error for one rank. |
| Reserved | 7:2 | roRead-only | 0x0 | Returns zeroes on reads. Caution: Do not write to this register field. |