DX5GCR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX5GCR0 (DDR_PHY) Register Description

Register NameDX5GCR0
Offset Address0x0000000C00
Absolute Address 0x00FD080C00 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x40200204
DescriptionDATX8 n General Configuration Register 0

DX5GCR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CALBYP31rwNormal read/write0x0Calibration Bypass: Prevents, if set, period measurement calibration
from automatically triggering after PHY initialization.
MDLEN30rwNormal read/write0x1Master Delay Line Enable: Enables, if set, the DATX8 master delay
line calibration to perform subsequent period measurements following
the initial period measurements that are performed after reset or on
when calibration is manually triggered. These additional
measurements are accumulated and filtered as long as this bit
remains high. This bit is combined with the common DATX8 MDL
enable bit.
CODTSHFT29:28rwNormal read/write0x0Configurable ODT(TE) phase shift applicable only when
DXSL*DXCTL2.CRDEN = 1`b1.
2`b00: no Phase shift on TE input to DQS PAD
2`b01: 0.5 SDR clock Phase shift on TE input to DQS PAD
2`b00: 1
SDR clock Phase shift on TE input to DQS PAD
2`b00: 1.5 SDR clock Phase shift on TE input to DQSPAD
RDDLY23:20rwNormal read/write0x2Number of Cycles ( in terms of ctl_rd_clk) to generate
ctl_dx_get_static_rd input for the respective by
t
e lane of the PHY.
Valid only when RDMODE is set as static response mode.
Reserved19:14roRead-only0x0Return zeroes on reads.
DQSNSEPDR13rwNormal read/write0x0DQSNSE Power Down Receiver: Powers down, if set, the input
receiver on the I/O for DQSN gate. This bit controls the PDRSE pin on
the PDIFF cell.
DQSSEPDR12rwNormal read/write0x0DQSSE Power Down Receiver: Powers down, if set, the input receiver
on the I/O for DQS gate. This bit controls the PDRSE pin on the
PDIFF cell.
RTTOAL11rwNormal read/write0x0RTT On Additive Latency: Indicates when the ODT control of DQ/DQS
SSTL I/Os is set to the value in DQODT/DQSODT during read cycles.
Valid values are:
0 = ODT control is set to DQSODT/DQODT almost two cycles before
read data preamble
1 = ODT control is set to DQSODT/DQODT almost one cycle before
read data preamble
RTTOH10:9rwNormal read/write0x1RTT Output Hold: Indicates the number of clock cycles (from 0 to 3)
after the read data postamble for which ODT control should remain
set to DQSODT for DQS or DQODT for DQ/DM before disabling it
(setting it to '0') when using dynamic ODT control. ODT is disabled
almost RTTOH clock cycles after the read postamble.
CPDRSHFT 8:7rwNormal read/write0x0Configurable PDR phase shift. applicable only when
DXSL*DXCTL2.CRDEN = 1`b1.
2`b00: no Phase shift on PDR input to DQS PAD
2`b01: 0.5 SDR clock Phase shift on PDR input to DQS PAD
2`b00: 1
SDR clock Phase shift on PDR input to DQS PAD
2`b00: 1.5 SDR clock Phase shift on PDR input to DQS PAD
DQSRPD 6rwNormal read/write0x0DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is
ORed with the common PDR configuration bit.
DQSGPDR 5rwNormal read/write0x0DQSG Power Down Receiver: Powers down, if set, the input receiver
on the I/O for DQS gate.
Reserved 4roRead-only0x0Return zeroes on reads.
DQSGODT 3rwNormal read/write0x0DQSG On-Die Termination: Enables, when set, the on-die termination
(TE pin) on the I/O for DQS gate. Note that in typical usage, DQSGOE
will always be on, rendering this control bit meaningless.
DQSGOE 2rwNormal read/write0x1DQSG Output Enable: Enables, when set, the output driver (OE pin)
on the I/O for DQS gate.
Reserved 1:0roRead-only0x0Return zeroes on reads.