DX5GCR0 (DDR_PHY) Register Description
Register Name | DX5GCR0 |
---|---|
Offset Address | 0x0000000C00 |
Absolute Address | 0x00FD080C00 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x40200204 |
Description | DATX8 n General Configuration Register 0 |
DX5GCR0 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CALBYP | 31 | rwNormal read/write | 0x0 | Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. |
MDLEN | 30 | rwNormal read/write | 0x1 | Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is combined with the common DATX8 MDL enable bit. |
CODTSHFT | 29:28 | rwNormal read/write | 0x0 | Configurable ODT(TE) phase shift applicable only when DXSL*DXCTL2.CRDEN = 1`b1. 2`b00: no Phase shift on TE input to DQS PAD 2`b01: 0.5 SDR clock Phase shift on TE input to DQS PAD 2`b00: 1 SDR clock Phase shift on TE input to DQS PAD 2`b00: 1.5 SDR clock Phase shift on TE input to DQSPAD |
RDDLY | 23:20 | rwNormal read/write | 0x2 | Number of Cycles ( in terms of ctl_rd_clk) to generate ctl_dx_get_static_rd input for the respective by t e lane of the PHY. Valid only when RDMODE is set as static response mode. |
Reserved | 19:14 | roRead-only | 0x0 | Return zeroes on reads. |
DQSNSEPDR | 13 | rwNormal read/write | 0x0 | DQSNSE Power Down Receiver: Powers down, if set, the input receiver on the I/O for DQSN gate. This bit controls the PDRSE pin on the PDIFF cell. |
DQSSEPDR | 12 | rwNormal read/write | 0x0 | DQSSE Power Down Receiver: Powers down, if set, the input receiver on the I/O for DQS gate. This bit controls the PDRSE pin on the PDIFF cell. |
RTTOAL | 11 | rwNormal read/write | 0x0 | RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are: 0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble 1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble |
RTTOH | 10:9 | rwNormal read/write | 0x1 | RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble. |
CPDRSHFT | 8:7 | rwNormal read/write | 0x0 | Configurable PDR phase shift. applicable only when DXSL*DXCTL2.CRDEN = 1`b1. 2`b00: no Phase shift on PDR input to DQS PAD 2`b01: 0.5 SDR clock Phase shift on PDR input to DQS PAD 2`b00: 1 SDR clock Phase shift on PDR input to DQS PAD 2`b00: 1.5 SDR clock Phase shift on PDR input to DQS PAD |
DQSRPD | 6 | rwNormal read/write | 0x0 | DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit. |
DQSGPDR | 5 | rwNormal read/write | 0x0 | DQSG Power Down Receiver: Powers down, if set, the input receiver on the I/O for DQS gate. |
Reserved | 4 | roRead-only | 0x0 | Return zeroes on reads. |
DQSGODT | 3 | rwNormal read/write | 0x0 | DQSG On-Die Termination: Enables, when set, the on-die termination (TE pin) on the I/O for DQS gate. Note that in typical usage, DQSGOE will always be on, rendering this control bit meaningless. |
DQSGOE | 2 | rwNormal read/write | 0x1 | DQSG Output Enable: Enables, when set, the output driver (OE pin) on the I/O for DQS gate. |
Reserved | 1:0 | roRead-only | 0x0 | Return zeroes on reads. |