DX5LCDLR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX5LCDLR0 (DDR_PHY) Register Description

Register NameDX5LCDLR0
Offset Address0x0000000C80
Absolute Address 0x00FD080C80 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Local Calibrated Delay Line Register 0

DX5LCDLR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Return zeroes on reads.
Reserved24:16roRead-only0x0Returns zeroes on reads.
Caution: Do not write to this register field.
Reserved15:9roRead-only0x0Return zeroes on reads.
WLD 8:0rwNormal read/write0x0Write Leveling Delay: Delay select for the write leveling (WL) LCDL for
the byte when in x8 mode