DX5LCDLR3 (DDR_PHY) Register Description
Register Name | DX5LCDLR3 |
---|---|
Offset Address | 0x0000000C8C |
Absolute Address | 0x00FD080C8C (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | DATX8 n Local Calibrated Delay Line Register 3 |
DX5LCDLR3 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | roRead-only | 0x0 | Return zeroes on reads. |
Reserved | 24:16 | roRead-only | 0x0 | Returns zeroes on reads. Caution: Do not write to this register field. |
Reserved | 15:9 | roRead-only | 0x0 | Return zeroes on reads. |
RDQSD | 8:0 | rwNormal read/write | 0x0 | Read DQS Delay: Delay select for the read DQS (RDQS) LCDL for the byte when in x8 mode |