DX8BDLR3 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8BDLR3 (DDR_PHY) Register Description

Register NameDX8BDLR3
Offset Address0x0000000F50
Absolute Address 0x00FD080F50 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Bit Delay Line Register 3

DX8BDLR3 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Return zeroes on reads.
DQ3RBD29:24rwNormal read/write0x0DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path
Reserved23:22roRead-only0x0Return zeroes on reads.
DQ2RBD21:16rwNormal read/write0x0DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path.
Reserved15:14roRead-only0x0Return zeroes on reads.
DQ1RBD13:8rwNormal read/write0x0DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path.
Reserved 7:6roRead-only0x0Return zeroes on reads.
DQ0RBD 5:0rwNormal read/write0x0DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path.