DX8BDLR5 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8BDLR5 (DDR_PHY) Register Description

Register NameDX8BDLR5
Offset Address0x0000000F58
Absolute Address 0x00FD080F58 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Bit Delay Line Register 5

DX8BDLR5 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:6roRead-only0x0Return zeroes on reads.
DMRBD 5:0rwNormal read/write0x0DM Read Bit Delay: Delay select for the BDL on DM read path.