DX8GCR2 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8GCR2 (DDR_PHY) Register Description

Register NameDX8GCR2
Offset Address0x0000000F08
Absolute Address 0x00FD080F08 (DDR_PHY)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDATX8 n General Configuration Register 2

DX8GCR2 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DXOEMODE31:16rwNormal read/write0x0Enables the OE mode values for DQ[7:0]. The bit [1:0] is for DQ[0],
bit[3:2] for DQ[1] etc. Valid values are:
00: OE Dynamic
01: OE always ON
10: OE always OFF
11:
RESERVED
DXTEMODE15:0rwNormal read/write0x0Enables the TE (ODT) mode values for DQ[7:0]. The bit [1:0] is for
DQ[0], bit[3:2] for DQ[1] etc. Valid values are:
00: TE (ODT) Dynamic
01: TE (ODT) always ON
10: TE (ODT) always OFF
11:
RESERVED