DX8LCDLR1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8LCDLR1 (DDR_PHY) Register Description

Register NameDX8LCDLR1
Offset Address0x0000000F84
Absolute Address 0x00FD080F84 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Local Calibrated Delay Line Register 1

DX8LCDLR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Return zeroes on reads.
Reserved24:16roRead-only0x0Returns zeroes on reads.
Caution: Do not write to this register field.
Reserved15:9roRead-only0x0Return zeroes on reads.
WDQD 8:0rwNormal read/write0x0Write Data Delay: Delay select for the write data (WDQ) LCDL for the
byte.
The WDQ LCDL register is automatically updated after DDL
Calibration (by Tck/4) and after Write leveling when write leveling is
performed.
Total delay should be written into this field. It overrides the delay set
by hardware.
Delay written in this field is converted to following two elements after
20 ctl_clk clock cycles:
1-Number of UI delays (pipelines) added to write dq path that can
be read from DxnGTR0.WDQSL field
2-The remainder of the delay, which is number of LCDL tap delays
(written delay - DxnGTR0.WDQSL * one UI period). It is smaller
than 1 UI delay and will be available to read in this field.
Reading this field returns the delay in item 2.
This field should be programmed only after running calibration.