DX8RSR3 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8RSR3 (DDR_PHY) Register Description

Register NameDX8RSR3
Offset Address0x0000000FDC
Absolute Address 0x00FD080FDC (DDR_PHY)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDATX8 n Rank Status Register 3

DX8RSR3 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved. Return zeroes on reads.
WLAERR15:0roRead-only0x0Write Latency Adjustment error: Indicates, for each of the system
ranks, that an error occurred in the WLA algorithm. This is for the
byte in x8 mode