DX8SL0DDLCTL (DDR_PHY) Register Description
Register Name | DX8SL0DDLCTL |
---|---|
Offset Address | 0x0000001424 |
Absolute Address | 0x00FD081424 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000002 |
Description | DATX8 0-1 DDL Control Register |
DX8SL0DDLCTL (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:27 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
DLYLDTM | 26 | rwNormal read/write | 0x0 | Delay Load Timing: Specifies the timing of the signal that is used to load the new delay select values into the LCDL when switching between ranks that have different delays. Valid values are: 1b0 = Assert the delay load signal on the first DDR clock cycle that has no activity (e.g. the first clock when the DQS gate signal is inactive). 1b1 = Assert the delay load signal one clock later than the first DDR clock cycle that has no activity (e.g. one clock later than the first clock when the DQS gate signal is inactive). |
DXDDLLDT | 25 | rwNormal read/write | 0x0 | DX DDL Load Type: Specifies how a new delay select value is applied to the delay line. This is only applicable to DDLs that have their delay select signals pipelined, such write leveling LCDL and read DQS gating LCDL. Valid values are: 1b0 = Apply the new delay select value to the delay line only when the delay select load signal is active and by first loading the delay select into the pipeline register 1b1 = Apply the delay select signal to the delay line directly, bypassing any pipeline registers and ignoring the delay select load signal |
Reserved | 24:23 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
DXDDLLD | 22:18 | rwNormal read/write | 0x0 | DATX8 DDL Delay Select Dynamic Load: Specifies whether the registers inside the DATX8 that hold the delay select signal of DATX8 DDL should be dynamically loaded only when the delay select changes or should be continuously (always) loaded. Valid values are: 1b0 = Delay select signal registers should be dynamically loaded only when the delay select signal has change and the delay load signal is high 1b1 = Delay select signal should be continuously (always) loaded on every clock cycle Different bits control different DATX DDLs as follows: DXDDLLD[0] = Write leveling delay load from controller DXDDLLD[1] = Read DQS gating delay load from controller DXDDLLD[2] = Write data delay load from PUB DXDDLLD[3] = Read path data strobe delay load from PUB DXDDLLD[4] = Read path data strobe # delay load from PUB |
DXDDLBYP | 17:2 | rwNormal read/write | 0x0 | DATX8 DDL Bypass: Specifies, if set to 1b1 that the DDL delay should be bypassed. Otherwise the DDL bypass is turned off. Different bits control different DATX8 DDLs as follows: * DXDDLYBYP[0] = Write path BDL delay bypass * DXDDLYBYP[1] = Read path BDL delay bypass * DXDDLYBYP[2] = Write path data strobe BDL delay bypass * DXDDLYBYP[3] = Write path data strobe # BDL delay bypass * DXDDLYBYP[4] = Unused * DXDDLYBYP[5] = Unused * DXDDLYBYP[6] = Power down receiver BDL delay bypass * DXDDLYBYP[7] = On-die termination enable BDL delay bypass * DXDDLYBYP[8] = DQ/DM output enable BDL delay bypass * DXDDLYBYP[9] = Write data LCDL delay bypass * DXDDLYBYP[10] = Read path data strobe LCDL delay bypass * DXDDLYBYP[11] = Read path data strobe # LCDL delay bypass * DXDDLYBYP[12] = Master delay LCDL delay bypass * DXDDLYBYP[13] = Write leveling LCDL delay bypass * DXDDLYBYP[14] = Read DQS gating LCDL delay bypass * DXDDLYBYP[15] = Read DQS gating status LCDL delay bypass |
DDLBYPMODE | 1:0 | rwNormal read/write | 0x2 | Controls DDL Bypass Modes. Valid values are: 2b00 = Normal dynamic control 2b01 = All DDLs bypassed 2b10 = No DDLs bypassed 2b11 = Reserved |