DX8SL0DQSCTL (DDR_PHY) Register Description
| Register Name | DX8SL0DQSCTL |
|---|---|
| Offset Address | 0x000000141C |
| Absolute Address | 0x00FD08141C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x01264000 |
| Description | DATX8 0-1 DQS Control Register |
DX8SL0DQSCTL (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | Returns zero on reads |
| RRRMODE | 24 | rwNormal read/write | 0x1 | Read Path Rise-to-Rise Mode: Indicates if set that the PHY mission mode is configured to run in rise-to-rise mode for the read path. Otherwise if not set the PHY mission mode for the read path is running in rise-to-fall mode. Note: Value programmed should be same across all the Slices |
| Reserved | 23:22 | roRead-only | 0x0 | Returns zero on reads |
| WRRMODE | 21 | rwNormal read/write | 0x1 | Write Path Rise-to-Rise Mode: Indicates if set that the PHY mission mode is configured to run in rise-to-rise mode for the write path. Otherwise if not set the PHY mission mode for the write path is running in rise-to-fall mode. |
| DQSGX | 20:19 | rwNormal read/write | 0x0 | DQS Gate Extension: Specifies if set that the read DQS gate will be extended. This should be set ONLY when used with DQS pulldown and DQSn pullup. Valid values are: 2b00 = Do not extend the gate 2b01 = Extend the gate by 1/2 tCK in both directions (but never earlier than zero read latency) 2b10 = Extend the gate earlier by 1/2 tCK and later by 2 * tCK (to facilitate LPDDR3 usage without training for systems supporting up to 800Mbps) 2b11 = Extend the gate earlier by 1/2 tCK and later by 3 * tCK (to facilitate LPDDR3 usage without training for systems supporting up to 1600Mbps) Note: Value programmed should be same across all the Slices |
| LPPLLPD | 18 | rwNormal read/write | 0x1 | Low Power PLL Power Down: Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the LPWAKEUP_THRSH. LPWAKEUP_THRSH is the Minimum threshold value of tlp_wakeup required to make phy go into low power mode by powering down PLL. The value of the dfi_lp_wakeup signal at the time that the dfi_lp_data_req&dfi_lp_ctrl_req signal is de-asserted sets the tlp_wakeup time. The value is in terms of number clock cycles. Refer Table 11 description of LPWAKEUP_THRSH for decoding details |
| LPIOPD | 17 | rwNormal read/write | 0x1 | Low Power I/O Power Down: Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. |
| Reserved | 16:15 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| QSCNTEN | 14 | rwNormal read/write | 0x1 | QS Counter Enable. Enables, if set, the counting of DQS edges for automatic shut-off of DQS gate. If turned off, the gate is closed using the gate signal from the PUB. Note: Value programmed should be same across all the Slices |
| UDQIOM | 13 | rwNormal read/write | 0x0 | Unused DQ I/O Mode: Selects SSTL mode (when set to 1b0) or CMOS mode (when set to 1b1) of the I/O for unused DQ pins. |
| Reserved | 12:10 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| DXSR | 9:8 | rwNormal read/write | 0x0 | Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. |
| DQSNRES | 7:4 | rwNormal read/write | 0x0 | DQS# Resistor: DQS_c glitch suppression resistor controls 0000 = Off 0001 = 2.5kOhm PD 0010 = 1.25kOhm PD 0011 = 830Ohm PD 0100 = 620Ohm PD 0101 = 500Ohm PD 0110 = 415Ohm PD 0111 = 355Ohm PD 1000 = Off 1001 = 2.5kOhm PU 1010 = 1.25kOhm PU 1011 = 830Ohm PU 1100 = 620Ohm PU 1101 = 500Ohm PU 1110 = 415Ohm PU 1111 = 355Ohm PU Pull-up/-down strength is independent of the ODT value selected by ZIOH[83:42]. The glitch suppression resistors are controlled by DQSR_c[3:0], OE, and TE. To use glitch suppression with unterminated DDR4, set TE=1 during read operations, but set ZIOH[83:42] to zero. |
| DQSRES | 3:0 | rwNormal read/write | 0x0 | DQS Resistor: DQS_t glitch suppression resistor controls 0000 = Off 0001 = 2.5kOhm PD 0010 = 1.25kOhm PD 0011 = 830Ohm PD 0100 = 620Ohm PD 0101 = 500Ohm PD 0110 = 415Ohm PD 0111 = 355Ohm PD 1000 = Off 1001 = 2.5kOhm PU 1010 = 1.25kOhm PU 1011 = 830Ohm PU 1100 = 620Ohm PU 1101 = 500Ohm PU 1110 = 415Ohm PU 1111 = 355Ohm PU Pull-up/-down strength is independent of the ODT value selected by ZIOH[83:42]. The glitch suppression resistors are controlled by DQSR_t[3:0], OE, and TE. To use glitch suppression with unterminated DDR4, set TE=1 during read operations, but set ZIOH[83:42] to zero. |