DX8SL0OSC (DDR_PHY) Register Description
Register Name | DX8SL0OSC |
---|---|
Offset Address | 0x0000001400 |
Absolute Address | 0x00FD081400 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00019FFE |
Description | DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register |
DX8SL0OSC (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:30 | roRead-only | 0x0 | Returns Zero on reads |
GATEDXRDCLK | 29:28 | rwNormal read/write | 0x0 | Enable Clock Gating for DX ddr_clk: Enables, when set, clock gating for power saving. Valid values are: Valid values are: 2b00 = Dynamic 2b01 = Always ON 2b10 = Always OFF 2b11 = Reserved |
GATEDXDDRCLK | 27:26 | rwNormal read/write | 0x0 | Enable Clock Gating for DX ctl_rd_clk: Enables, when set, clock gating for power saving. Valid values are: 2b00 = Dynamic 2b01 = Always ON 2b10 = Always OFF 2b11 = Reserved |
GATEDXCTLCLK | 25:24 | rwNormal read/write | 0x0 | Enable Clock Gating for DX ctl_clk: Enables, when set, clock gating for power saving. Valid values are: 2b00 = Dynamic 2b01 = Always ON 2b10 = Always OFF 2b11 = Reserved |
CLKLEVEL | 23:22 | rwNormal read/write | 0x0 | Selects the level to which clocks will be stalled when clock gating is enabled in PHY. Valid values are: 2b00 = Clocks will stall to static level 0 2b01 = Clocks will stall to static level 1 2b10 - 2b11= Clocks will toggle at slow speed. |
LBMODE | 21 | rwNormal read/write | 0x0 | Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode. Note: Value programmed should be same across all the Slices |
LBGSDQS | 20 | wtcReadable, write a 1 to clear | 0x0 | Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period). This bit must only be used when initializing the GSDQS 180 degree offset for IO assisted gating mode. This bit is self clearing. Note: Value programmed should be same across all the Slices |
LBGDQS | 19:18 | rwNormal read/write | 0x0 | Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are: 2b00 = DQS gate is always on 2b01 = DQS gate training will be triggered by the PUB 2b10 = DQS gate is set manually using software 2b11 = Reserved Note: Value programmed should be same across all the Slices During mission mode, this field must be at its default setting During BIST AC and DX simultaneous loopback, this field should be set to 2`b00 to get overlapping AC and DX traffic. |
LBDQSS | 17 | rwNormal read/write | 0x0 | Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: 1b0 = PUB sets the read DQS LCDL to 0; DQS is already shifted 90 degrees by write path 1b1 = The read DQS shift is set manually through software Note: Value programmed should be same across all the Slices |
PHYHRST | 16 | rwNormal read/write | 0x1 | PHY High-Speed Reset: A write of 1b0 to this bit resets the AC and DATX8 macros without resetting PUB RTL logic. This bit is not self- clearing and a 1b1 must be written to de-assert the reset. |
PHYFRST | 15 | rwNormal read/write | 0x1 | PHY FIFO Reset: A write of 1b0 to this bit resets the AC and DATX8 FIFOs without resetting PUB RTL logic. This bit is not self- clearing and a 1b1 must be written to de-assert the reset. |
DLTST | 14 | rwNormal read/write | 0x0 | Delay Line Test Start: A write of 1b1 to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to 1b0 before the measurement can be re- retriggered. Note: Value programmed should be same across all the Slices |
DLTMODE | 13 | rwNormal read/write | 0x0 | Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Note: Value programmed should be same across all the Slices |
Reserved | 12:11 | rwNormal read/write | 0x3 | Returns zeroes on reads. Caution: Do not write to this register field. |
OSCWDDL | 10:9 | rwNormal read/write | 0x3 | Oscillator Mode Write-Data Delay Line Select: Selects which of the two write data (WDQ) LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: 2b00 = No WDQ LCDL is active 2b01 = DDR WDQ LCDL is active 2b10 = CTL WDQ LCDL is active 2b11 = Both LCDLs are active |
Reserved | 8:7 | rwNormal read/write | 0x3 | Returns zeroes on reads. Caution: Do not write to this register field. |
OSCWDL | 6:5 | rwNormal read/write | 0x3 | Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: 2b00 = No WL LCDL is active 2b01 = DDR WL LCDL is active 2b10 = CTL WL LCDL is active 2b11 = Both LCDLs are active |
OSCDIV | 4:1 | rwNormal read/write | 0xF | Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: 4b0000 = Divide by 1 4b0001 = Divide by 4 4b0010 = Divide by 8 4b0011 = Divide by 16 4b0100 = Divide by 32 4b0101 = Divide by 64 4b0110 = Divide by 128 4b0111 = Divide by 256 4b1000 = Divide by 512 4b1001 = Divide by 1024 4b1010 = Divide by 2048 4b1011 = Divide by 4096 4b1100 = Divide by 8192 4b1101 = Divide by 16384 4b1110 = Divide by 32768 4b 1111 = Divide by 65536 |
OSCEN | 0 | rwNormal read/write | 0x0 | Oscillator Enable: Enables, if set, the delay line oscillation. |