DX8SL1DXCTL1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8SL1DXCTL1 (DDR_PHY) Register Description

Register NameDX8SL1DXCTL1
Offset Address0x0000001468
Absolute Address 0x00FD081468 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00040000
DescriptionDATX8 0-1 DX Control Register 1

DX8SL1DXCTL1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Reserved. Return zeroes on reads.
DXCALCLK24rwNormal read/write0x0DATX Calibration Clock Select: Valid values are:
1b0 = ddr_clk (x4 clock) is used for delay line calibration
1b1 = ctl_clk (x1 clock) is used for delay line calibration
Note: Value programmed should be same across all the Slices
DXRCLKMD23rwNormal read/write0x0DATX8 read Clock Mode: Valid values are:
1b0 = Read clock (ctl_rd_clk) is generated from DATX8 ctl_rd_clk
pin
1b1 = Read clock (ctl_rd_clk) is generated from DATX8 ctl_clk pin
Note: Value programmed should be same across all the Slices
Reserved22roRead-only0x0Reserved. Return zeroes on reads.
DXDTOSEL21:20rwNormal read/write0x0DATX8 Digital Test Output Select: This is used to select the DATX8
internal signals that should be driven on the two DATX8 digital test
outputs (phy_status[3:2]) signals.
Valid values for DATX8 digital test output bit 0 (phy_status[2]) are:
2b00 = DQS gate status bit 0
2b01 = DQS gate enable output (after gate output LCDL)
2b10 = DQS clock (qs_clk)
2b11 = CTL delayed clock (ctl_dly_clk)
Valid values for digital test out bit 1[1] (phy_status[3]) are:
2b00 = DQS gate status bit 1
2b01 = DQS gate enable input (after gate status (input) LCDL)
2b10 = DQS delayed clock (qs_n_dly_clk)
2b11 = DDR delayed clock (ddr_dly_clk)
DXGSMD19rwNormal read/write0x0Read DQS gating status mode: Indicates if set that the read DQS
gating status that is stored in the DQS read FIFO is the gate input.
Otherwise, if not set, the registered DQS gate status is stored in the
FIFO
Note: Value programmed should be same across all the Slices
DXQSDBYP18rwNormal read/write0x1Read DQS/DQS# delay load bypass mode. Valid values are:
1b0 = Automatically bypass the read DQS/DQS# LCDLs when its
delay select signal is being dynamically changed (i.e. drive the
LCDL bypass signal to the same value as the delay select load
signal)
1b1 = Dont automatically bypass the read DQS/DQS# LCDLs
when its delay select signal is being dynamically changed (i.e. dont
drive the LCDL bypass signal to the same value as the delay select
load signal)
NOTE: This feature (no auto-bypassmode) is automatically
disabled when using delay select direct control mode
(DXPHYMODE[3])
Note: Value programmed should be same across all the Slices
DXGDBYP17rwNormal read/write0x0Read DQS gate delay load bypass mode. Valid values are:
1b0 = Automatically bypass the read DQS gate LCDL when its
delay select signal is being dynamically changed (i.e. drive the
LCDL bypass signal to the same value as the delay select load
signal)
1b1 = Dont automatically bypass the read gate DQS LCDL when
its delay select signal is being dynamically changed (i.e. dont drive
the LCDL bypass signal to the same value as the delay select load
signal)
NOTE: This feature (no auto-bypassmode) is automatically
disabled when using delay select direct control mode
(DXPHYMODE[3])
Note: Value programmed should be same across all the Slices
DXTMODE16rwNormal read/write0x0DATX8 Test Mode: This is used to enable special test mode in the
DATX8 macro. Valid values are:
1b0 = Normal mode
1b1 = Test mode
Note: Value programmed should be same across all the Slices
Reserved15:0roRead-only0x0Reserved. Return zeroes on reads.