DX8SL1IOCR (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8SL1IOCR (DDR_PHY) Register Description

Register NameDX8SL1IOCR
Offset Address0x0000001470
Absolute Address 0x00FD081470 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 0-1 I/O Configuration Register

DX8SL1IOCR (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31roRead-only0x0Reserved. Return zeroes on reads.
DXDACRANGE30:28rwNormal read/write0x0PVREF_DAC REFSEL range select
DXIOM24:22rwNormal read/write0x0I/O Mode: I/O Mode select
000 = DDR3, DDR3L, DDR3U mode
001 = CMOS mode
010 = DDR4, LPDDR3 mode
011 = Reserved
100 = LPDDR4 mode
101 = Reserved
110 = Reserved
111 = Reserved