DX8SL1PLLCR5 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8SL1PLLCR5 (DDR_PHY) Register Description

Register NameDX8SL1PLLCR5
Offset Address0x0000001458
Absolute Address 0x00FD081458 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDAXT8 0-1 PLL Control Register 5 (Type B PLL Only)

DX8SL1PLLCR5 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved. Return zeroes on reads.
PLLCTRL_103_96 7:0rwNormal read/write0x0Connects to bits [103:96] of the PLL general control bus PLL_CTRL