DX8SL3PLLCR0 (DDR_PHY) Register Description
| Register Name | DX8SL3PLLCR0 |
|---|---|
| Offset Address | 0x00000014C4 |
| Absolute Address | 0x00FD0814C4 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x001C0000 |
| Description | DAXT8 0-1 PLL Control Register 0 |
DX8SL3PLLCR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PLLRST | 30 | rwNormal read/write | 0x0 | PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self- clearing and a 1b0 must be written to de-assert the reset. |
| PLLPD | 29 | rwNormal read/write | 0x0 | PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a 1b0 must be written to de-assert the power-down. |
| RSTOPM | 28 | rwNormal read/write | 0x0 | Reference Stop Mode. Connects to pin REF_STOP_MODE. Valid values are: 1b0 = Default, normal mode 1b1 = Reference stop mode is enabled |
| FRQSEL | 27:24 | rwNormal read/write | 0x0 | PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that support up 2400 Mbps are: 4b0000:PLL reference clock (ctl_clk/REF_CLK) range 560MHz to 600MHz 4b0001:PLL reference clock (ctl_clk/REF_CLK) range 471MHz to 560MHz 4b0010:PLL reference clock (ctl_clk/REF_CLK) range 396MHz to 471MHz 4b0011:PLL reference clock (ctl_clk/REF_CLK) range 332MHz to 396MHz 4b0100:PLL reference clock (ctl_clk/REF_CLK) range 279MHz to 332MHz 4b0101:PLL reference clock (ctl_clk/REF_CLK) range 235MHz to 279MHz 4b0110:PLL reference clock (ctl_clk/REF_CLK) range 197MHz to 235MHz 4b0111:PLL reference clock (ctl_clk/REF_CLK) range 166MHz to 197MHz 4b1000 - 4b1111:RESERVED |
| RLOCKM | 23 | rwNormal read/write | 0x0 | Relock Mode: Enables, if set, rapid relocking mode. Connects to pin RELOCK_MODE on the PLL. |
| CPPC | 22:17 | rwNormal read/write | 0xE | Charge Pump Proportional Current Control. Connects to pin CPPROP_CNTRL on the PLL. Valid values for PHYs that support up 2400 Mbps are: 6b000111:PLL reference clock (ctl_clk/REF_CLK) range 560MHz to 600MHz 6b001000:PLL reference clock (ctl_clk/REF_CLK) range 471MHz to 560MHz 6b001001:PLL reference clock (ctl_clk/REF_CLK) range 396MHz to 471MHz 6b001010:PLL reference clock (ctl_clk/REF_CLK) range 332MHz to 396MHz 6b000110:PLL reference clock (ctl_clk/REF_CLK) range 279MHz to 332MHz 6b001000:PLL reference clock (ctl_clk/REF_CLK) range 235MHz to 279MHz 6b001001:PLL reference clock (ctl_clk/REF_CLK) range 197MHz to 235MHz 6b001010:PLL reference clock (ctl_clk/REF_CLK) range 166MHz to 197MHz All other settings: RESERVED |
| CPIC | 16:13 | rwNormal read/write | 0x0 | Charge Pump Integrating Current Control. Connects to pin CP_INT_CTRL on the PLL. Valid values for PHYs that support up 2400 Mbps are: 4b0000:PLL reference clock (ctl_clk/REF_CLK) range 332MHz to 600MHz 4b0001:PLL reference clock (ctl_clk/REF_CLK) range 235MHz to 332MHz 4b0010:PLL reference clock (ctl_clk/REF_CLK) range 197MHz to 235MHz 4b0011:PLL reference clock (ctl_clk/REF_CLK) range 166MHz to 197MHz 4b0100 - 4b1111:RESERVED |
| GSHIFT | 12 | rwNormal read/write | 0x0 | Gear Shift: Enables, if set, rapid locking mode. Connects to pin GEAR_SHIFT on the PLL. |
| Reserved | 11:9 | roRead-only | 0x0 | Reserved. Return zeroes on reads |