DX8SL4DXCTL1 (DDR_PHY) Register Description
Register Name | DX8SL4DXCTL1 |
---|---|
Offset Address | 0x0000001528 |
Absolute Address | 0x00FD081528 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00040000 |
Description | DATX8 0-1 DX Control Register 1 |
DX8SL4DXCTL1 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
DXCALCLK | 24 | rwNormal read/write | 0x0 | DATX Calibration Clock Select: Valid values are: 1b0 = ddr_clk (x4 clock) is used for delay line calibration 1b1 = ctl_clk (x1 clock) is used for delay line calibration Note: Value programmed should be same across all the Slices |
DXRCLKMD | 23 | rwNormal read/write | 0x0 | DATX8 read Clock Mode: Valid values are: 1b0 = Read clock (ctl_rd_clk) is generated from DATX8 ctl_rd_clk pin 1b1 = Read clock (ctl_rd_clk) is generated from DATX8 ctl_clk pin Note: Value programmed should be same across all the Slices |
Reserved | 22 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
DXDTOSEL | 21:20 | rwNormal read/write | 0x0 | DATX8 Digital Test Output Select: This is used to select the DATX8 internal signals that should be driven on the two DATX8 digital test outputs (phy_status[3:2]) signals. Valid values for DATX8 digital test output bit 0 (phy_status[2]) are: 2b00 = DQS gate status bit 0 2b01 = DQS gate enable output (after gate output LCDL) 2b10 = DQS clock (qs_clk) 2b11 = CTL delayed clock (ctl_dly_clk) Valid values for digital test out bit 1[1] (phy_status[3]) are: 2b00 = DQS gate status bit 1 2b01 = DQS gate enable input (after gate status (input) LCDL) 2b10 = DQS delayed clock (qs_n_dly_clk) 2b11 = DDR delayed clock (ddr_dly_clk) |
DXGSMD | 19 | rwNormal read/write | 0x0 | Read DQS gating status mode: Indicates if set that the read DQS gating status that is stored in the DQS read FIFO is the gate input. Otherwise, if not set, the registered DQS gate status is stored in the FIFO Note: Value programmed should be same across all the Slices |
DXQSDBYP | 18 | rwNormal read/write | 0x1 | Read DQS/DQS# delay load bypass mode. Valid values are: 1b0 = Automatically bypass the read DQS/DQS# LCDLs when its delay select signal is being dynamically changed (i.e. drive the LCDL bypass signal to the same value as the delay select load signal) 1b1 = Dont automatically bypass the read DQS/DQS# LCDLs when its delay select signal is being dynamically changed (i.e. dont drive the LCDL bypass signal to the same value as the delay select load signal) NOTE: This feature (no auto-bypassmode) is automatically disabled when using delay select direct control mode (DXPHYMODE[3]) Note: Value programmed should be same across all the Slices |
DXGDBYP | 17 | rwNormal read/write | 0x0 | Read DQS gate delay load bypass mode. Valid values are: 1b0 = Automatically bypass the read DQS gate LCDL when its delay select signal is being dynamically changed (i.e. drive the LCDL bypass signal to the same value as the delay select load signal) 1b1 = Dont automatically bypass the read gate DQS LCDL when its delay select signal is being dynamically changed (i.e. dont drive the LCDL bypass signal to the same value as the delay select load signal) NOTE: This feature (no auto-bypassmode) is automatically disabled when using delay select direct control mode (DXPHYMODE[3]) Note: Value programmed should be same across all the Slices |
DXTMODE | 16 | rwNormal read/write | 0x0 | DATX8 Test Mode: This is used to enable special test mode in the DATX8 macro. Valid values are: 1b0 = Normal mode 1b1 = Test mode Note: Value programmed should be same across all the Slices |
Reserved | 15:0 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |