DX8SL4PLLCR3 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8SL4PLLCR3 (DDR_PHY) Register Description

Register NameDX8SL4PLLCR3
Offset Address0x0000001510
Absolute Address 0x00FD081510 (DDR_PHY)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDAXT8 0-1 PLL Control Register 3 (Type B PLL Only)

DX8SL4PLLCR3 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PLLCTRL_63_3231:0rwNormal read/write0x0Connects to bits [63:32] of the PLL general control bus PLL_CTRL