DX8SLbDQSCTL (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8SLbDQSCTL (DDR_PHY) Register Description

Register NameDX8SLbDQSCTL
Offset Address0x00000017DC
Absolute Address 0x00FD0817DC (DDR_PHY)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionDATX8 0-8 DQS Control Register

DX8SLbDQSCTL (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25woWrite-only0Reserved. Return zeroes on reads.
RRRMODE24woWrite-only0Read Path Rise-to-Rise Mode
Reserved23:22woWrite-only0Reserved. Return zeroes on reads.
WRRMODE21woWrite-only0Write Path Rise-to-Rise Mode
DQSGX20:19woWrite-only0DQS Gate Extension
LPPLLPD18woWrite-only0Low Power PLL Power Down
LPIOPD17woWrite-only0Low Power I/O Power Down
Reserved16:15woWrite-only0Reserved. Return zeroes on reads.
QSCNTEN14woWrite-only0QS Counter Enable
UDQIOM13woWrite-only0Unused DQ I/O Mode
Reserved12:10woWrite-only0Reserved. Return zeroes on reads.
DXSR 9:8woWrite-only0Data Slew Rate
DQSNRES 7:4woWrite-only0DQS# Resistor
DQSRES 3:0woWrite-only0DQS Resistor