DX8SLbDXCTL2 (DDR_PHY) Register Description
| Register Name | DX8SLbDXCTL2 |
|---|---|
| Offset Address | 0x00000017EC |
| Absolute Address | 0x00FD0817EC (DDR_PHY) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | DATX8 0-8 DX Control Register 2 |
DX8SLbDXCTL2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | woWrite-only | 0 | Returns zero on reads |
| CRDEN | 23 | woWrite-only | 0 | Configurable Read Data Enable: 1`b0: DFI timing parameter trddata_en = RL-4 1`b1: DFI timing parameter trddata_en = RL-6 Note: Value programmed should be same across all the Slices. |
| POSOEX | 22:20 | woWrite-only | 0 | OE extension during post-amble 3'b000: OE is on for 0.5 dram clock during DQS post-amble. 3'b001: OE is on for 1.0 dram clock during DQS post-amble. 3'b010: OE is on for 1.5 dram clock during DQS post-amble. 3'b011: OE is on for 2.0 dram clock during DQS post-amble. 3'b100: OE is on for 2.5 dram clock during DQS post-amble. 3'b101: OE is on for 3.0 dram clock during DQS post-amble. 3'b110: OE is on for 3.5 dram clock during DQS post-amble. 3'b111: OE is on for 4.0 dram clock during DQS post-amble. Note: Value programmed should be same across all the Slices |
| PREOEX | 19:18 | woWrite-only | 0 | OE extension during pre-amble 2'b00: OE is on for 1.0 dram clock during DQS preamble. 2'b01: OE is on for 1.5 dram clock during DQS preamble. 2'b10: OE is on for 2.0 dram clock during DQS preamble. 2'b11: OE is on for 2.5 dram clock during DQS preamble. Note: Value programmed should be same across all the Slices The value programmed should correspond to the Write Preamble WR-PRE setting in MR1 register for LPDDR4 mode or MR4.WRP for DDR4 mode. For example if MR1.WR-PRE bit is set to \q1\q for 2 * tCK Write Preamble, then PREOEX must be programmed to 2`b10. |
| Reserved | 17 | woWrite-only | 0 | Returns zero on reads |
| IOAG | 16 | woWrite-only | 0 | I/O assisted Gate Select 1'b0: IO assisted gating not selected 1'b1: IO assisted gating selected Note: IO assisted gating is applicable only for static read response mode which is enabled only when DXSL8DXCTL.RDMODE == 2'b11 Note: Value programmed should be same across all the Slices |
| IOLB | 15 | woWrite-only | 0 | I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: 1b0 = Loopback is after output buffer; output enable must be asserted 1b1 = Loopback is before output buffer; output enable is don't care |
| Reserved | 14:13 | woWrite-only | 0 | Returns zero on reads |
| LPWAKEUP_THRSH | 12:9 | woWrite-only | 0 | Low Power Wakeup Threshold: If dfi_lp_wakeup is greater than this threshold value, PLLs will be powered down when entering DFI low power mode. The value of the dfi_lp_wakeup signal at the time that the dfi_lp_ctrl_req or dfi_lp_data_req signal is asserted sets the tlp_wakeup time. Valid values in terms of number clock cycles are: 4b0000 = 16 cycles 4b0001 = 32 cycles 4b0010 = 64 cycles 4b0011 = 128 cycles 4b0100 = 256 cycles 4b0101 = 512 cycles 4b0110 = 1024 cycles 4b0111 = 2048 cycles 4b1000 = 4096 cycles 4b1001 = 8192 cycles 4b1010 = 16384 cycles 4b1011 = 32768 cycles 4b1100 = 65536 cycles 4b1101 = 131072 cycles 4b1110 = 262144 cycles 4b1111 = Unlimited cycles LPWAKEUP_THRSH calculation: MINIMUM LPWAKEUP CYCLES = pll_lock_time / ctl_clk_period + MDL calibration cycles where, MDL calibration cycles = N * DDL calibration cycles N is Decoded value of PGCR1.FDEPTH. Example, With tCK= 938 ps; ctl_clk = 1876 ps; and PGCR1.FDEPTH = 2b10: From the PGCR1 register description, FDEPTH=2b10 decodes to a depth of 8. Pll_lock_time from PLL spec is 25us. So LPWAKEUP_THRSH = 25 ns / 1876 ps + 8 * (800 cycles) = 13326 + 6400 = 19726 cycles Setting LPWAKEUP_THRSH to 4b1010 would trigger PLL power down for tlp_wakeup value of 32768 cycles and above; which meets the calculations for MINIMUM LPWAKEUP CYCLES of 19726 cycles Note: Value programmed should be same across all the Slices |
| RDBI | 8 | woWrite-only | 0 | Read Data Bus Inversion Enable: when set to 1b1 (and MR5[12] is set to 1b1 in DDR4 mode and MR3[6] is set to 1`b1 in LPDDR4 mode). PUB performs data bus inversion on the DRAM read data; when set to 1b0, the read data and DM_n/DBI_n signal are passed on to the controller as is. Note: Value programmed should be same across all the Slices |
| WDBI | 7 | woWrite-only | 0 | Write Data Bus Inversion Enable: when set to 1b1 (and MR5[11:10] is set to 2b10 in DDR4 and MR3[7] is set to 1`b1 in LPDDR4 mode), PUB generates the write DBI on the DM_n/DBI_n signal. Not supported with write CRC. Note: Value programmed should be same across all the Slices |
| PRFBYP | 6 | woWrite-only | 0 | Pub Read FIFO Bypass: When set to 1b1, the read capture FIFO inside PUB is bypassed. Valid values are: 1b0 = FIFO used to capture read data from PHY 1b1 = No FIFO used to capture read data from PHY. This mode is ONLY valid when static response mode is enabled. Note: Value programmed should be same across all the Slices |
| RDMODE | 5:4 | woWrite-only | 0 | DATX8 Receive FIFO Read Mode. Valid values are: 2b00 = 2 stage synchronizer async FIFO 2b01 = 3 stage synchronizer async FIFO 2b10 = 4 stage synchronizer async FIFO 2b11 = static read response (To be used for pull-up terminated LPDDR3 and DDR4 interfaces only.) Note: The static response mode should be selected only when system is in IDLE. The static response mode must be OFF when Initialization and Training operation is performed. Only Static read response mode is supported (2`b11) during DCU and BIST tests Value programmed should be same across all the Slices |
| DISRST | 3 | woWrite-only | 0 | Disables the Read FIFO reset: When set, read receive FIFO can't be reset from ctl_dx_rdfifo_rstn input. Valid values are: 1b0 = RX Read FIFO is reset when ctl_dx_rxfifo_rstn is LOW. 1b1 = RX Read FIFO can't be reset by ctl_dx_rxfifo_rstn Note: Value programmed should be same across all the Slices |
| DQSGLB | 2:1 | woWrite-only | 0 | Read DQS Gate I/O Loopback: Controls the loopback signal (LB) on the I/O that is used to drive the read DQS gate. This also selects the type of gating used since it controls the signal driven on the DI output of this PDQSG I/O. Valid values are: 2b00 = Pad-sided loopback of gate signal from PUB is used for gating 2b01 = Core-sided loopback of gate signal from PUB is used for gating 2b10 = DQS# SE signal from PDIFF I/O is is used for gating 2b11 = DQS SE signal from PDIFF I/O is used for gating Note: Value programmed should be same across all the Slices |
| Reserved | 0 | woWrite-only | 0 | Returns zero on reads |