DX8SLbOSC (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DX8SLbOSC (DDR_PHY) Register Description

Register NameDX8SLbOSC
Offset Address0x00000017C0
Absolute Address 0x00FD0817C0 (DDR_PHY)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionDATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register

DX8SLbOSC (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30woWrite-only0Reserved. Return zeroes on reads.
GATEDXRDCLK29:28woWrite-only0Enable Clock Gating for DX ddr_clk
GATEDXDDRCLK27:26woWrite-only0Enable Clock Gating for DX ctl_rd_clk
GATEDXCTLCLK25:24woWrite-only0Enable Clock Gating for DX ctl_clk
CLKLEVEL23:22woWrite-only0Selects the level to which clocks will be stalled when clock gating is enabled.
LBMODE21woWrite-only0Loopback Mode
LBGSDQS20woWrite-only0Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
LBGDQS19:18woWrite-only0Loopback DQS Gating
LBDQSS17woWrite-only0Loopback DQS Shift
PHYHRST16woWrite-only0PHY High-Speed Reset
PHYFRST15woWrite-only0PHY FIFO Reset
DLTST14woWrite-only0Delay Line Test Start
DLTMODE13woWrite-only0Delay Line Test Mode
Reserved12:11woWrite-only0Reserved. Caution, do not write to this register field.
OSCWDDL10:9woWrite-only0Oscillator Mode Write-Data Delay Line Select
Reserved 8:7woWrite-only0Reserved. Caution, do not write to this register field.
OSCWDL 6:5woWrite-only0Oscillator Mode Write-Leveling Delay Line Select
OSCDIV 4:1woWrite-only0Oscillator Mode Division
OSCEN 0woWrite-only0Oscillator Enable